ASIC architecture
Interface partitioning, clock domains, memory hierarchy and power architecture defined before RTL.
Discuss thisDesign & SimulationVLSI and ASIC design
VLSI and ASIC design
for problems off-the-shelf parts cannot reach.
Some products outgrow standard parts: the interface is unusual, the volume makes custom silicon worthwhile, or the feature simply does not exist off the shelf. We design that logic — architecture, RTL, verification and physical implementation — and support you through tape-out.
- Architecture & RTL
- Verification & sign-off
- Tape-out support
When custom silicon makes senseStandard parts stop being
Standard parts stop being
the cheapest answer.
Custom silicon is usually justified by one of three things: a feature no available part provides, a unit cost that only falls below a volume threshold, or a requirement such as size, power or interface timing that cannot be met by configuring an existing device.
It is also the most expensive commitment in electronics. We help you test the business case against alternatives first, and if custom is right, we design it so verification and physical implementation are planned from the start rather than retrofitted.
Verification is the real schedule risk. RTL written quickly but verified late is the main cause of slipped tape-outs, so the verification plan is agreed before implementation begins.
- 01Business case tested first
Custom silicon is compared against module, FPGA and configuration alternatives before you commit.
- 02Architecture before RTL
Interface, clocking, memory and power architecture decided up front, because these are expensive to change later.
- 03Verification planned early
Verification strategy, coverage and sign-off criteria agreed before implementation, not after.
- 04Sign-off aware
Timing, power and area closure considered during design rather than discovered at the end.
- Alternatives comparedModule, FPGA and configuration options assessed before committing to custom silicon.
- Architecture firstInterfaces, clock domains, memory hierarchy and power strategy settled before RTL is written.
- Verification plannedCoverage goals and sign-off criteria defined up front, which is what keeps tape-out on schedule.
- Physical design includedTiming, power and area closure addressed as part of implementation.
What we deliver
VLSI and ASIC design services
Engagements range from an architecture study to a full flow through to tape-out and post-silicon bring-up.
RTL design
Synthesizable RTL written to a defined coding standard, with reusable and parameterised blocks.
Discuss thisDesign verification
Simulation, formal checks and coverage-driven verification with agreed sign-off criteria.
Discuss thisPhysical design
Synthesis, place and route, timing and power closure against the target process and constraints.
Discuss thisDFT & testability
Scan, test coverage and production test considerations built into the design from the start.
Discuss thisTape-out & post-silicon
Tape-out support, bring-up, debug and yield analysis once silicon returns.
Discuss thisWhat is included in scope
Scope is agreed in writing before work starts, so deliverables and responsibilities are clear.
- Feasibility & alternativesCustom silicon compared against module, FPGA and configuration options, with cost modelled.
- Architecture specificationInterfaces, clocking, memory, power domains and performance targets written down and agreed.
- RTL implementationSynthesizable RTL developed to a coding standard, with design reviews at block level.
- Verification & sign-offVerification plan, coverage closure and sign-off criteria agreed, then executed to completion.
- Physical implementationSynthesis, place and route, timing and power closure, DFT insertion and sign-off.
- Tape-out and bring-upTape-out support, post-silicon bring-up, debug and yield issue analysis.
Capabilities
VLSI and ASIC capability
The flow is planned as a whole, because the decisions that affect tape-out schedule are made at the start, not at the end.
Interface design
Custom bus, protocol and mixed-signal interfaces where no standard controller fits.
Data processing logic
Pipelines, filters, codecs, encryptors and data-path logic written as parameterised RTL.
Memory & clock architecture
Memory hierarchies, clock domain crossing and reset strategies planned up front.
Low-power design
Power domains, gating and clocking strategies considered from the architecture stage.
Verification engineering
Coverage-driven verification, formal property checks and regression management.
DFT & production test
Scan insertion, test coverage and production test planning built in from the start.
Physical implementation
Synthesis, place and route with timing, power and area closure managed deliberately.
Post-silicon debug
Bring-up, debug and yield analysis once first silicon is available.
Where a discrete or FPGA solution may be enough, start with cost & BOM analysis. Board-level consequences of a custom device are handled in circuit design.
Our process
How a custom design proceeds
Feasibility, architecture, implementation, verification, then physical design and tape-out.
Feasibility & specification
Business case tested against alternatives and the design specification written and agreed.
Design specificationArchitecture
Interfaces, clocking, memory and power domains designed and reviewed before RTL begins.
Architecture specRTL & verification
RTL implemented block by block against a verification plan with coverage tracking.
Verified RTLPhysical design & tape-out
Synthesis, place and route, timing and power closure, then tape-out and bring-up.
Tape-out and silicon
Technologies
Design flow and technologies
Process and toolchain choices follow the target volume, performance and cost rather than familiarity.
- HDL designSynthesisable RTL with a defined coding standard and review discipline
- VerificationSimulation, formal property checking and coverage-driven regression
- Physical designSynthesis, place and route, timing and power analysis against target constraints
- InterfacesCustom bus, protocol, mixed-signal and high-speed interface logic
- Low-power & DFTPower domains, gating, scan insertion and production test planning
- Process nodesSelected against volume, performance, cost and foundry availability for your product
Process selection is a long-term commitment. We weigh unit cost at your expected volume, mask and NRE cost, tool availability and the foundry's record on yield for your design.
Industries
Built for your industry’s environment.
Temperature, vibration, electrical transients and certification needs differ by sector, and they are captured during discovery rather than after the first build.
Telecom & networking
Equipment and connectivity for networks, access hardware and connected infrastructure.
Telecom & networkingIndustrial
Control panels, motor drives, gateways and automation hardware for continuous operation.
IndustrialAutomotive
In-cabin electronics, LED drivers and control units designed around automotive electrical and thermal expectations.
AutomotiveEnergy & power
Monitoring, metering, conversion and control electronics for energy and power systems.
Energy & powerHealthcare
Diagnostic and monitoring devices designed with patient safety and compliance in mind.
HealthcareDefence
Rugged, secure and mission-critical systems with controlled supply and documentation.
DefenceCapability examplesSee the engineering problem.
See the engineering problem.
Imagine the possibilities.
The scenarios below illustrate the kind of work we do — they are not published client case studies or measured results. Ask us about relevant experience for your product.
Illustrative · Volume product
A controller for a high-volume device
Challenge: A standard MCU could not meet the interface and cost targets at volume.
Approach: Architecture optimised for the exact interface, with power and area closed against the target process.
Explore electronics developmentIllustrative · Signal processing
A dedicated data-path accelerator
Challenge: A flexible processor used far more power than the workload actually required.
Approach: Fixed-function logic designed for the specific data path, verified with coverage-based sign-off.
Explore electronics developmentIllustrative · Legacy replacement
Replacing logic in an ageing product
Challenge: A controller was no longer available and could not be reordered.
Approach: Its function re-implemented as custom logic, verified against the original behaviour before tape-out.
Explore component sourcingFrequently asked questionsGood questions.
Good questions.
Clear starting points.
What buyers usually want to know before scoping this kind of work.
Ask about your requirements →When is custom silicon the right choice?
Typically when a required feature does not exist in an available part, when unit cost only falls below a threshold at your volume, or when size, power or interface timing cannot be met by configuring standard devices.
Do you help decide whether we need custom silicon?
Yes. We compare custom against module, FPGA and configuration options and model the cost, so the decision is made on evidence rather than enthusiasm.
What does the flow include?
Feasibility and specification, architecture, RTL implementation, verification with coverage closure, physical design with timing and power closure, and tape-out and post-silicon support.
How do you reduce tape-out risk?
Architecture and the verification plan are agreed before implementation begins, design reviews happen at block level, and sign-off criteria are defined up front rather than negotiated at the end.
Which process nodes do you work with?
The process is selected against your expected volume, performance and cost targets, together with mask cost, NRE, tool availability and foundry yield record. We advise rather than default to one node.
Can you work with our existing RTL?
Yes. We can review existing RTL for structure, coding standard compliance, verification quality and synthesizability, then continue the design or prioritise the changes needed.
Related services
Design & Simulation
Explore the rest of the programme, or get in touch about this service directly.
Start your projectLet’s test whether custom silicon
Let’s test whether custom silicon
is really the answer.
Tell us what the part needs to do, your expected volume and what is blocking the current solution. We will be direct if a module or FPGA makes more sense.
No complete specification needed. A short brief of your product and goals is enough to start.
What happens next?
- Share your product goal, application and current stage.
- Discuss the components, interfaces and constraints that matter.
- Agree a practical next step and the scope for a proposal.